Optimization of Work-Center Cycle Time Target Setting in a Semiconductor Wafer Fab

Abstract

In this paper the problem of assigning target cycle times at operation level in a semiconductor wafer fab, where target end-to-end-delays are given, is considered.
In the original position allowed waiting times are assigned at processing stations proportional to the square root of processing times.
We apply the fairness principle which claims that waiting times should be proportional to processing times at so-called machine resource pools. To match overall cycle time targets the normalization constants are adjusted using LP and QP methods.